italian version

Aims :

To know the principles of operation of the CMOS digital circuits. To analyze and to synthetize combinatorial and sequential logical circuits at different levels of abstraction.

Topics :

Inverter. Inverter characteristics: DC characteristics, noise margins, propagation delay. Fundamentals of electronic devices. First principles of solid state electronics: band diagram, p-n junction. MOS capacitor: threshold voltag. The MOSFET: Body effect, channel lenght modulation, DC characteristics. Parasitic capacitances. Elementary CMOS logic gates. NMOS Inverter, CMOS Inverter: DC characteristic, noise margins, logic threshold. Inverter CMOS switching characteristics: inverter capacitances, rise time, fall time, propagation delays, max switching frequency. Example of calculus of CMOS inverter parameters in 0.35mm technology. Power dissipation: static and dinamic case, "short circuit" power dissipation, Product Delay-Power. CMOS Buffer.
Complex CMOS logic gates. CMOS static logic gates: NAND, NOR, XOR, XNOR. Mirror circuit: XOR, XNOR. DC characteristic, project formulas. Output capacitance. NAND-NOR comparison. CMOS transient: RC approximation, Elmore method. NANDN, NORN logic gates: project formulas. CMOS Tristate. Tristate gates applications. Elementary BJT logic gates. TTL inverter: input stage, inverter, output stage, transfer characteristic. DC characteristic: voltages, currents, power dissipation. NAND-NOR TTL. TTL-CMOS intefacing. BiCMOS inverter.
Combinatorial circuits. Comparators, binary decoders. multiplexer, demultiplexer. PLD: logic array, AND, OR. PLA. Wired-and, Wired-or. Transmission Gates: nFET and pFET switch, Clock feedthrough, CMOS switch. Multiplexer with 2 or 4 inputs, simulations and layout, XOR e XNOR.
Sequential circuits. Flip-flop: FF SR, FF D, FF T, Latch, FF D in Master/Slave configuration. Finite state systems (FSS), binary FSS. Synchronous and asynchronous circuits. synthesis methodologies .
Memories. SRAM: memory cell, sense amplifier. CMOS SRAM: 6 transistor cell. Column sense amplifier. DRAM: 4 transistor cell, 1 transistor cell. EPROM, EEPROM, FLASH.
ASIC Design Guidelines. Synchronous circuits. Clock buffering. Gated clock. Asynchronous reset . Shift register. Asynchronous inputs. Delay line and monostables. Bistables elements.
I2C bus.


Textbooks :

Paolo Spirito, Elettronica Digitale, Mc Graw Hill Italia, seconda edizione, 2002.
Richard C. Jaeger, Travis N. Blalock, Elettronica Digitale, seconda edizione, McGraw-Hill, 2005.
John P. Uyemura, CMOS Logic Circuit Design, Kluwer Academic Publisher, 1999.

Exam :

Written and oral test.

Tutorial Session :

from monday to thursday
from 15:00 to16:00